Purpose of the development: The adaptive spatio-temporal signal processing module is designed to improve the basic tactical and technical characteristics of civil and military radars in the presence of interference.

Recommended application field: Radar stations for airspace control and air traffic control for military and civilian purposes.

Advantages over analogues: As calculations and semi-natural experiments show, in comparison with existing interference protection systems, the developed module allows increasing the range of detection of air targets and the accuracy of measuring their coordinates under conditions of combined interference by 20-25%.

The development stage readiness: Pre-production model is made

Description of the development:
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Protection against combined interference is based on the formation of highly efficient (most likely) parameter estimates of the factors of factorized matrix representations that are inverse to the correlation interference matrix and their regularized varieties. This technology is implemented on a unified structural-algorithmic basis of adaptive array filters (ARF), suitable for use in adaptive protection systems from both masking active and passive interference, as well as for solving other problems of spatio-temporal signal processing in radars for various purposes.In the prototype adaptive digital spatio-temporal signal processing module on a modern element base, a quasi-Newton algorithm for adapting a radar to Gaussian interference with previously unknown parameters based on an adaptive grating filter (ARF) is implemented. The module consists of a series-connected hardware-software unit (APB) of adaptive digital spatial processing (ADSP) of signals against a background of noise interference and an APB of adaptive digital time processing (ACBO) of signals against a background of passive interference.APB ATSPO is based on the Xilinx V7 EK-V7-VC707 debug board with a high-speed gate array chip (FPGA) of the XC7VX485T-2FFG1761C type, which made it possible to implement algorithms with parallelizing processes. This significantly (by one or two orders of magnitude) improved the performance of the ADSP unit and its efficiency, including when the compensation modules of the phased array antenna are not identical.APB ACVO is based on the Texas Instruments MDSEVM6678L debug board with the DSP TMS320C6678 high-speed chip of the eight-core signal processor (SP). Each of the 8 cores operates at a clock frequency of 1 GHz and ensures the speed of operations with a fixed point of each core up to 44.8 GMAC, and with a floating point - up to 22.4 GFLOP. They have two high-speed memory (cache) level L1 with a capacity of 32 KB each, local memory level L2 512 KB and 4 MB common for all cores of RAM.

Certif 47.49

corresponds technical description
Reguires revision

Possibility of transfer abroad:
Combinated reduction to industrial level

Photo

Country Ukraine

For additional information turn to:
E-mail: gal@uintei.kiev.ua